1. Field of the Invention
The present invention relates generally to amplifiers in analog-to-digital converters (ADCs), and particularly to a current-mode folding amplifier characterized by the number of folds, N, and the fold size IF.
2. Description of the Related Art
Analog-to-digital converters (ADCs) are one of the most important sub-circuits of any digital system that is intended to interface with the analog world. Because of their ubiquitous presence, ADCs with high speed, compact form factor, low voltage, and low power are highly desirable. There are different architectures of ADCs available in the literature, among which full flash ADC is the fastest and simplest one. However, this kind of ADCs requires 2N−1 comparators and 2N resistors, where N is the number of bits, which causes such topology to be impractical for higher number of bits. One of the solutions is a folding ADC, which reduces the number of comparators, and hence the power and size of the ADC, with a minimum compromise in the conversion speed. Folding ADCs require a folding amplifier, and for accuracy of conversion, saw-tooth folding characteristics are highly desirable. Moreover, current-mode implementation can offer low voltage and faster response. Thus, current-mode folding amplifiers with saw-tooth transfer characteristics and faster response are of interest.
Conventional voltage-mode folding amplifiers are built around differential amplifiers. Different folding ADCs have been reported utilizing voltage-mode folding amplifiers, which had either sinusoidal or triangular folding characteristics. Folding ADCs with such folding characteristics cause error in digitization and need extra error correction/compensation circuitry. Moreover, such voltage-mode folding amplifiers will not be suitable for low voltage application due to the non-linearity of the differential amplifiers used for folding amplifier realization.
Thus, a current-mode folding amplifier solving the aforementioned problems is desired.